Optimizing Blocks in an SoC Using Symbolic Code-Statement Reachability Analysis
Journal
15th Asia and South Pacific Design Automation Conference (ASP-DAC 2010)
Pages
787-792
Date Issued
2010-01
Author(s)
Abstract
Optimizing blocks in a System-on-Chip (SoC) circuit is becoming more and more important nowadays due to the use of third-party Intellectual Properties (IPs) and reused design blocks. In this paper, we propose techniques and methodologies that utilize abundant external don't-cares that exist in an SoC environment for block optimization. Our symbolic code-statement reachability analysis can extract don't-care conditions from constrained-random testbenches or other design blocks to identify unreachable conditional blocks in the design code. Those blocks can then be removed before logic synthesis is performed to produce smaller and more power-efficient final circuits. Our results show that we can optimize designs under different constraints and provide additional flexibility for SoC design flows.
SDGs
Type
conference paper