A Quadratic Error Compensation in High-Speed 8-bit Current-Steering Digital to Analog Converter
Date Issued
2009
Date
2009
Author(s)
Huang, Chien-Chun
Abstract
This thesis proposes an 8-bit 1GHz digital-to-analog converter with a segmented current steering architecture that consists of two parts, the upper 5-bit thermometer code and the lower 3-bit binary-weighted code. The design not only keeps the advantages of current steering architecture, but also consumes lower power. The DAC architecture is implemented by the proposed switching sequence. The new switching sequence divides the upper 5-bit current source into eight unary current source to compensate quadratic error and also uses integral non-linear (INL) bounded algorithm to optimize the INL characteristic. This DAC has been implemented in a 90nm 1P9M mixed-signal CMOS process provided by UMC, with active area of 0.013mm2 and total area including PADs is 0.415mm2.The INL and differential non-linear (DNL) are 0.19 and 0.26 LSB, respectively. The spurious-free dynamic range (SFDR) is 49.2dB when the update rate is 1GHz and the input frequency is 9.25MHz. The power consumption is 8.2mW with a supply voltage of 1V.
Subjects
digital-to-analog converter
integral non-linear
integral non-integral bounded algorithm
differential non-linear
spurious-free dynamic range
Type
thesis
File(s)![Thumbnail Image]()
Loading...
Name
ntu-98-J95921038-1.pdf
Size
23.32 KB
Format
Adobe PDF
Checksum
(MD5):a178b2b6a1e1e52907d3451e8aa1a266