An efficient architecture for two-dimensional discrete wavelet transform
Resource
VLSI Technology, Systems, and Applications, 1999. International Symposium on
Journal
International Symposium on VLSI Technology, Systems, and Applications, 1999
Pages
-
Date Issued
1999-06
Date
1999-06
Author(s)
Wu, Po-Cheng
DOI
N/A
Abstract
This paper proposes an efficient architecture for the two-dimensional discrete wavelet transform (2-D DWT). The proposed architecture includes a transform module, a RAM module, and a multiplexer. In the transform-module, we employ the polyphase decomposition technique to the decimation filters of stage 1, and the coefficient folding technique to the decimation filters of stage 2. The RAM size is N/2/spl times/N/2. In comparison with other 2-D DWT architectures, the advantages of the proposed architecture are the near 100% hardware utilization, fast computation time, regular data flow, and low complexity control circuit, making this architecture suitable for next generation image compression systems.
Type
journal article
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