Fault-tolerant Router with Built-in Self-test/Self-diagnosis and Fault-isolation Circuits for 2D-mesh Based Chip Multiprocessor
Journal
International Journal of Electrical Engineering
Journal Volume
16
Journal Issue
3
Pages
1126-1135
Date Issued
2009
Author(s)
Abstract
A fault-tolerant router design (20-path router) is proposed to reduce the impacts of faulty routers for 2D-mesh based chip multiprocessor systems. In our experiments, the OCNs using 20PRs can reduce 75.65% ~ 85.01% unreachable packets and 7.78% ~ 26.59% latency in comparison with the OCNs using generic XY routers.
Type
journal article