A performance evaluation procedure for a class of growable ATM switches
Resource
Parallel Architectures, Algorithms and Networks, 1994. (ISPAN) International Symposium on
Journal
International Symposium on Parallel Architectures, Algorithms and Networks, 1994. (ISPAN)
Pages
-
Date Issued
1994-12
Date
1994-12
Author(s)
Tsai, Zsehong
Yu, Kangyei
Lai, Feipei
DOI
N/A
Abstract
We propose a modular ATM switching network by modifying the original delta network. It is composed of several stages of switching modules, and all the switching modules are of the same type of basic building block. In order to improve the performance, the channel group connecting the switching modules in all stages are expanded to contain more then one link. The switching system is in fact a discrete-time queueing network, and each output of a particular switching module is modeled as a finite buffer, multi-server queue with multiple cell arrival streams. We obtain a general performance evaluation procedure for such a multi-stage, self-routing switching system.>
Type
journal article
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