Power-Efficient Successive-Approximation Register Analog-to-Digital Converter
Date Issued
2016
Date
2016
Author(s)
Liao, Bo-Shi
Abstract
Today analog to digital converter (ADC) plays an important role in electronic systems. It is a bridge between nature analog environment and digital world. Recently requirement of low power application grows gradually, especially in wireless communication, sensor network and biomedical system. As the result, how to decrease the power dissipation of ADC become big issues. In different types of ADC, successive approximation register (SAR) ADC does not have op-amplifier and most blocks are only digital circuits, so SAR ADC can achieve the low power specification. In the field of low power SAR ADC, an 12-bit 10MS/s single-channel SAR and 7-bit 2GS/s calibration-free time-interleaved ADC are presented. This thesis first proposes an energy-efficient high resolution SAR ADC with small unit capacitance and simple controller logic. In order to save digital power, it combined with arbitrary capacitor array, which tolerates errors of dynamic offset and capacitor settling in MSBs during conversion and a differential control logic circuit are proposed to decrease the circuit complexity. The technique are verified by TSMC 1P6M3X1Z1U 40nm Low Power CMOS process. This work operates at 10MS/s in 0.9V supply voltage. Its power dissipation is only 36.9μW and gets 10.05 bit ENOB performance after off-chip calibration with low-frequency input. As the result, the peak FoM performance is 3.48fJ/conversion-step. In the second design, in order to solve offset mismatch, an offset-compensation algorithm is proposed. It transforms offset mismatch to nonlinearity, and creates redundancy range to compensate it. In addition, a front-end track-and-hold circuit is implemented in order to eliminate time skew mismatch. This time-interleaved ADC in 55nm CMOS technology post-simulation achieves an ENOB of 6.8 and consumes 24.8mW. It results in a FoM of 117fJ/conversion-step.
Subjects
ADC
SAR ADC
low power
high speed
time-interleaved
offset mismatch
time skew mismatch
calibration-free
Type
thesis