Digital Logic Analyzer Design
Date Issued
2006
Date
2006
Author(s)
Liao, Chun-Hao
DOI
zh-TW
Abstract
As the development of digital system progresses day by day, engineers must rely on logic analyzer to analyze and understand a lot of signals and program codes. Moreover, engineers do not always work in the company. It is necessary to take the logic analyzer to customers for debug service such PC-based logic analyzer with good performance is required.
Instrument type of logic analyzer has good performance with high frequency bandwidth, high sample rate, high operation speed, high speed of trigger latch function, width memory depth…etc. However, it is so expensive and too heavy that it is difficult to carry. The price of Pocket type (or called PC-based type) of logic analyzer is much cheaper and is easy to carry. However, the performance of Pocket type of logic analyzer is limited. Since there is no microprocessor inside Pocket type of logic analyzer such that frequency bandwidth, sample rate, operation speed, trigger latch function, memory depth…etc are not to suitable for measurements for most high speed digital system nowadays.
In this paper, the design and implementation of a logic analyzer with high performance, easy to carry and low cost are focused. CPLD is used for considerations of cost and design risk. Technically, we use different DLL and data transforms methods to perform high sampling rate and high speed triggering latch function without high operation speed microprocessor. Our design is based on CPLD so that the cost of components is less expensive than that of with high operation speed microprocessor method. In addition, we use SDRAM for storing device for memory depth. According to development of SDRAM, the capacity and access speed of SDRAM are progressing constantly. So using SDRAM as the design of memory depth will meet the requirement of digital system in the future.
Subjects
邏輯分析儀
取樣
觸發擷取
鎖相倍頻
Logic analyzer
Sample rate
Trigger latch function
DLL
Type
thesis