Thermal stress aware design for stacking IC with through glass via
Journal
International Microsystems, Packaging, Assembly, and Circuits Technology Conference
Pages
133-136
Date Issued
2012
Author(s)
Chien, J.-H.
Yu, H.
Lung, C.-L.
Chang, H.-C.
Tsai, N.-Y.
Chou, Y.-F.
Chen, P.-H.
Chang, S.-C.
Kwai, D.-M.
Abstract
Stacking die technology using interposer with through-substrate-via technology has attracted a lot of attention due to various advantages in performance and integration. Interposers with through-glass-vias (TGVs) are widely studied due to their excellent electrical properties. However, a high temperature environment during the fabrication process of TGV leads to uncontrollable thermal expansion, which then causes a serious reliability problem. In this paper, we present an efficient algorithm to place micro bumps to reduce stress surrounding TGVs in appropriate positions that can minimize the total number of micro bumps needed. Our simulated results show that significant reduction on the maximum stress can be achieved. Not only the proposed design can lower the maximum temperature of the hotspot, but improve the thermal uniformity of the test chip.
SDGs
Type
conference paper