Electrical Characteristics of Via Discontinuity and Manufacturing Solution Space Analysis with the Neural Networks-Based Approach
Date Issued
2006
Date
2006
Author(s)
Hsu, Ku-Teng
DOI
zh-TW
Abstract
As the data rates increase into the multi-gigabit range, the effect of via discontinuities on printed circuit board becomes non-negligible. Lumped-circuit models for via structures are usually constructed from their geometries to understand the signal integrity issues. The π-type equivalent circuit of a via consists of two excess capacitances and an excess inductance. Capacitance and inductance values can be computed using a full-wave solver. Full-wave characterization can lead to accurate results, however, it takes the tremendous computational efforts and is not practical for an efficient circuit design.
In recent years, the electromagnetically trained artificial neural network (EM-ANN) approaches have gained the recognition. Accurate and fast neural models can be developed from the simulated EM data. These neural models can speed up the circuit design with the accuracy compared to that of a full-wave solver. This thesis describes a methodology for designing a low-reflection passive component such as via structures or similar structures. The multi-layer neural network is trained to fast predict the impedance of vias based on the physical dimensions. Once the EM-ANN model has been trained, it is easy to derive a whole of impedance profile over the desired physical dimension range. The via structures are chosen with reference to the design solution space by the matching impedance thus to the microstrip line from two interconnected sides. The solution space is demonstrated by the time-domain simulations and measurements, accordingly.
Subjects
類神經網路
連通柱
不連續結構
阻抗匹配
製程解空間
neural network
via
discontinuity
matching impedance
design solution space
Type
thesis
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