An accurate time-domain current waveform simulator for VLSI circuits
Resource
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.
Journal
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design
Pages
Proceeding-s
Date Issued
1994-03
Date
1994-03
Author(s)
Wang, Jyh-Herng
Fan, Jen-Teng
Feng, Wu-Shiung
DOI
N/A
Abstract
A new charge-based current model for CMOS gates is presented in this paper. The current during a transition consists of three components: one occurs when the input changes and the others exist only when the output changes. So, this model can generate current waveform with negative values, like SPICE. These three components are characterized by triangular functions with four parameters which can be easily obtained after timing simulation. When comparing the results obtained by using SPICE with those by our model, we find agreement, especially on the time points at which maximum current occurs.>
SDGs
Type
journal article
File(s)![Thumbnail Image]()
Loading...
Name
00326818.pdf
Size
411.58 KB
Format
Adobe PDF
Checksum
(MD5):cafde595ddf79f5b7bf6b68a39ed6181