Mixed-Size Placement Prototyping Based on Reinforcement Learning with Semi-Concurrent Optimization
Part Of
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Start Page
893
End Page
899
ISBN (of the container)
979-840070635-6
ISBN
[9798400706356]
Date Issued
2025-01-20
Author(s)
Cheng-Yu Chiang
Yi-Hsien Chiang
Chao-Chi Lan
Yang Hsu
Che-Ming Chang
Shao-Chi Huang
Sheng-Hua Wang
Hung-Ming Chen
DOI
10.1145/3658617.3697730
Abstract
Placement plays a crucial role in modern chip design, aiming to determine the positions of circuit blocks (macros and standard cells). Traditional data structure-centric heuristics often yield suboptimal placement prototypes, ineffectively guiding downstream mixed-size analytical placement to find the desired results for modern large-scale designs. Recent works have showcased the potential of reinforcement learning (RL) to enhance chip placement by training a policy to place macros as a board game. However, placing macros and fixing them in the earlier stages without sufficient information often incurs undesired solutions. This paper proposes a novel RL-based mixed-size placer with iteratively moving the blocks to characterize dense rewards and comprehensive layout information in each step. We further introduce a semi-concurrent moving mechanism to learn the collaborative dynamics among actions on a subset of blocks at each step. We integrate continuous action spaces to develop a deep Q network-based model for learning the semi-concurrent moving policy to derive the proposed moving strategy. Compared with the state-of-the-art methods, experimental results show that our RL-based placer achieves the best placement quality based on commonly used mixed-size placement benchmarks.
Event(s)
0th Asia and South Pacific Design Automation Conference, ASP-DAC 2025Tokyo
Publisher
ACM
Type
conference paper