Design and Implementation of Clock Generators in Nanoscale CMOS Processes
Date Issued
2010
Date
2010
Author(s)
Chang, Jung-Yu
Abstract
With the progress of the CMOS technologies, the demand of high-speed communication system grows gradually. The most important part of the communication system is clocking system, which directly determines the speed and system performance. However, the leakage problem in 90nm or 65nm processes will degrade the performance of the clock systems, and the subject of this dissertation is to solve the problems of clock generators in nanoscale processes.
Phase-locked loops (PLLs) and delay-locked loops (DLLs) have been typically employed for the clock generation. PLLs are usually used in the high speed applications due to their clock multiplication architecture, but it is hard to integrate a PLL on a chip because the area of loop filter is large. To reduce the physical size of a PLL, the capacitor in loop filter is usually realized by the MOS capacitor. However, in nanoscale processes, the large leakage current due to oxide tunneling current will degrade the performance of a PLL seriously, and the severe channel length modulation will produce large reference spur. These problems must be taken into account when the clock generators are implemented in nanoscale processes. Compared with PLLs, DLLs usually have better jitter performance and small chip area. However, the limited bandwidth of the voltage-controlled delay line (VCDL) makes the DLLs hard to operate at high frequency. .
In this dissertation, two leakage compensated circuits are proposed to solve the leakage current caused by MOS capacitor. By detecting the phase error between the reference signal and feedback clock, the corresponding compensated current can be produced in first work. However, the open loop structure after compensation makes that the first work can’t track the variations of temperature or supply voltage. The background compensation has been proposed to solve this problem. It can keep compensation when the temperature or supply voltage changes. Then a spur suppression technique is presented to solve the spur problem caused by subthreshold leakage or CP mismatch. By redistributing the frequency of spur, the amplitude of reference spur can be reduced.
Finally, a 20GHz DLL is presented. Using the injection locked frequency divider, the speed limitation of the VCDL can be relaxed. Moreover, a new start-up circuit is also proposed for high frequency application.
In nanoscale processes, the leakage problems in PLLs and limited bandwidth in DLLs make the design of clock generators hardly. This dissertation proposes four solutions to solve these problems.
Subjects
Phase-locked loop
delay-locked loop
leakage compensation
spur
Type
thesis
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