A 40~550MHz harmonic-free all-digital delay-locked loop using a variable SAR algorithm
Journal
IEEE Journal of Solid-State Circuits
Journal Volume
42
Journal Issue
2
Pages
361-373
Date Issued
2007-02
Author(s)
Rong-Jyi Yang
Abstract
A wide-range all-digital delay-locked loop (ADDLL) is presented to achieve low jitter, low power and process immunity. The variable successive approximation register-controlled algorithm is proposed to eliminate the harmonic-locking issue in wide-range operation. It can also achieve the fast-locking property and closed-loop operation. With the balanced edge combiner, the ADDLL outputs a synchronous clock with the duty cycle close to 50% when the duty cycle of the input clock varies from 20% to 80%. Fabricated in 0.18 μm CMOS technology, the ADDLL maintains a fixed one input clock cycle latency from 40 MHz to 550 MHz without the harmonic-locking issue. It dissipates 12.6 mW from a 1.8 V supply at 550 MHz. The measured root-mean-square and peak-to-peak jitters at 550 MHz are 1.5 ps and 12 ps, respectively. © 2007 IEEE.
SDGs
Type
journal article