Bundle-Updatable SRAM-Based TCAM Design for OpenFlow-Compliant Packet Processor
Journal
IEEE Transaction on Very Large Scale Integration (VLSI) Systems (TVLSI)
Journal Volume
27
Journal Issue
6
Pages
1095-1101
Date Issued
2019
Author(s)
Abstract
Static random-access memory (SRAM)-based ternary content-addressable memories (TCAMs) emulate TCAM functions with high throughput at low cost. However, the implementation of SRAMbased TCAM as a rule table in network switches tends to prolong updating latency, which can cause a false packet routing. This brief proposes a novel low-latency bundle-updatable TCAM (BU-TCAM) scheme that uses binary tree-based prefix encoding (BPE) to support singleand multiple-rule updating in a software-defined networking/OpenFlow network. The proposed encoding method transforms the original ternary rule data into a binary code word and determines the range of overlap in SRAM addresses to facilitate updating. This greatly decreases latency in cases where multiple rules are required to update on an SRAMbased TCAM. We implemented an emulated 64 × 32-bit TCAM of the proposed design on a Xilinx ZC-706 field-programmable gate array. The proposed scheme reduced updating latency by 79.6%, compared with a conventional updating structure, which had only 9.8% and 23% increases in LUTs and registers overhead, respectively.
Type
journal article