Continuous time digitizer utilizing multiphase sampling technique
Journal
IEEE Nuclear Science Symposium Conference Record
Journal Volume
1
Pages
374-378
Date Issued
2007
Author(s)
Abstract
In this paper, the new architecture of a high-speed continuous time digitizer is proposed. With the aid of a two-level multiphase sampling technique, the time digitizer can use only 16 delay cells and DFFs to perform the flash-type conversion of 64- stage interpolation. The time digitizer can obtain 78ps resolution with a reference frequency running at 200 MHz. The continuous input clock frequency can be up to 250 MHz. The test chip is fabricated in TSMC 0.18 μm 1P6M mixed mode process. The layout area occupies 1.08 mm 2 . The DNL is within -0.62 ∼ +0.51 and INL within -0.99 ∼ +0.98. A novel clock multiplier is also introduced to provide multiphase generation with the frequency output range within 0.64 ∼ 1.8 GHz.
SDGs
Type
conference paper