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Design and Application of Low Power Pipelined and SAR Analog-to-Digital Converters
Date Issued
2009
Date
2009
Author(s)
Fang, Po-Hsiang
Abstract
As the rapid growth on the development of the wireless communication system, the requirement for the ADC that connect the digital and analog circuits becomes stricter and stricter. In this thesis, two kinds of ADCs are implemented that contain power-saving techniques.n Chapter 3 of this thesis, a low power SAR ADC is presented which uses the advantage of the fully differential structure to decrease the requirement of capacitors, that makes the chip area smaller while get the same resolution as the traditional circuit. The chip is fabricated by TSMC 0.35um 2P4M CMOS technology and the measurement results will be shown. n Chapter 4, a pipelined ADC is introduced which uses opamp current reuse technique to decrease the power dissipation without summing node reset problem. As a result, we can get the advantage of pipelined ADC that has high operation speed without massive power consumption.
Subjects
ADC
SAR
pipelined
Type
thesis
File(s)
No Thumbnail Available
Name
ntu-98-R96943050-1.pdf
Size
23.32 KB
Format
Adobe PDF
Checksum
(MD5):34dff308040a461d079fbe0d0780434e