Design and Implementation of a Distributed Video Decoder
Date Issued
2014
Date
2014
Author(s)
Ho, Meng-Hsuan
Abstract
In conventional video coding, lots of coding techniques were proposed to exploit redundancy of the spatial and temporal signals in the encoder. These coding techniques are focused on compressing video data as high as possible, such as MEPG (Moving Picture Experts Group) and H.26X proposed by International Telecommunication Union. These conventional techniques tried to extremely reduce spatial and temporal redundancies, so all the computing efforts were majorly spent on the encoder. Conventional video coding is not suitable for the situations where little encoders and big decoders are used, like wireless video sensors that have a low computing capability and need a low power consumption. To meet the requirement of a low-complexity and low-power encoder, a new video coding paradigm, distributed video coding, based on Slepian-Wolf Theorem and Wyner-Ziv Theorem, was proposed. In this Thesis, we design and implement a distributed video decoder which is majorly composed of LDPCA, correlation noise modeling, soft input computation, and side information creation. Our proposed DVC decoder, implemented in TSMC 90nm GUTM process technology, can meet the requirement of decoding a QCIF video with a speed of 30fps. The maximum operation frequency is 100MHz, the chip area is 4.67 mm2, and gate count is 690K.
Subjects
Distributed Video Decoder
LDPCA Decoder
Side Information Creation
Type
thesis
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