A Fast-Acquisition Demodulation Scheme for 2.4GHz Wireless DSSS Transceiver VLSI
Resource
International Symposium on VLSI Technology System and Application, Taipei, Taiwan(1999.06)
Journal
1999 International Symposium on VLSI Technology Systems and Applications Proceedings of Technical Papers (Cat No 99TH8453)
Pages
227-230
Date Issued
1999-06
Date
1999-06
Author(s)
Wang, C. K.
Abstract
In this paper, a CMOS cell based system VLSI design for Direct-Sequence Spread-Spectrum (DSSS) wireless LAN transceiver is presented. In addition, an efficient and fast-acquisition demodulation scheme is proposed to use in the receiver architecture. Implementation and testing results are also given. The proposed demodulation scheme can help to positively combine the received signal energy of multipaths so that the detection performance is improved by 3 dB in a typical frequency-selective indoor wireless communication environment. The proposed architecture can synchronize the PN code in 30 /spl mu/s and the chip size is 5600/spl times/4600 /spl mu/m/sup 2/. It can be operated from 3.3 V to 5 V and the power consumption ranges from 189 mW to 250 mW respectively.
SDGs
Type
conference paper