H.264/AVC熵解碼器之設計與實作
Design and Implementation of an Entropy Decoder for H.264/AVC
Date Issued
2005
Date
2005
Author(s)
Wu, Guan-Lin
DOI
en-US
Abstract
The coding performance of H.264/AVC has greater improvement than previous video standards. It adopts Context-Based Adaptive Binary Arithmetic Coding (CABAC) and variable length coding as its entropy coding. In variable length coding of H.264/AVC, context-based adaptive and trailing ones are the important coding skills to increase coding performance. Its compression rate is very close to CABAC but the computing complexity is much lower. With the recent development of communication, computer, and multimedia, the real-time processing of huge data is required for video phone, video conference and high definition television applications. So, high performance video compression technology is needed.
In this Thesis, we propose a high throughput variable length decoder circuit for H.264/AVC baseline profile. A whole entropy decoder for H.264/AVC baseline profile is also presented. As the name indicates, codewords are of variable length. Furthermore, there is no boundary information for detecting the end or beginning of the codeword. These characteristics complicate the design and hardware realizations. We observe the coding steps and lookup tables of CAVLC. Then we propose a multiple-symbol decoder for CAVLC without increasing too many circuit area and critical path.
A prototype chip is implemented to verify the design of proposed CAVLC decoder circuit. The chip is fabricated in UMC 0.18μm 1P6M CMOS process through CIC. The die size is 1.291 x 1.292 mm2, and gate count is about 10k. The maximum operation frequency obtained from gate level simulation is 100 MHz. And the maximum operation frequency from post layout simulation is 71.43 MHz. The format of test image is CIF. In general, the average number of total coefficients need to be decoded in one block is not over 5. In this condition, we can decode one block about 30 cycles. Thus, one macroblock (MB) decoding needs about 480 cycles to complete. In H.264 standard, Level 3.1 needs a maximum MB processing rate of 108,000 MB per second. That is, we need an operation frequency of 480x 108,000= 51,840,000 clocks/s=51.84 MHz, which is lower than our maximum post layout frequency. The format of processing image in Level 3.1 is 1280 x 720 x 30 fps. Power consumption of our design is about 16.8707mW at 1.8 V, and the number of pads is 58.
Subjects
熵
可變長度編碼
視訊壓縮
entropy
VLC
variabl length coding
CAVLC
H.264
AVC
Type
thesis
File(s)![Thumbnail Image]()
Loading...
Name
ntu-94-R92943067-1.pdf
Size
23.31 KB
Format
Adobe PDF
Checksum
(MD5):26e4a8b92d089619c64b2de1fcaa6a3d