A 0.8-8 GHz 9.7 mW analog-digital dual-loop adaptive-bandwidth DLL based multi-phase clock generator

Resource

Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European

Journal

30th European Solid-State Circuits Conference, 2004. ESSCIRC 2004

Pages

-

Date Issued

2004-09

Date

2004-09

Author(s)

Wang, Chorng-Kuang

DOI

DOI

N/A

URI

Type

journal article

File(s)

Name

01356696.pdf

Size

307.04 KB

Format

Adobe PDF

Checksum

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