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Very-Low-Voltage and IDDQ Testing of Amorphous Silicon TFT Digital NMOS Circuits
Date Issued
2008
Date
2008
Author(s)
Shen, Shiue-Tsung
Abstract
This thesis presents a strategy, including very-low-voltage (VLV) and quiescentpower supply current (IDDQ) testing, for reliability screening of amorphous silicon thin-film transistor (a-Si TFT) digital NMOS circuits manufactured with 8μm a-Si process by Industrial Technology Research Institute. In addition, 200 seconds and 30V stress is applied for burn-in to verify the experimental results of VLV and IDDQ testing. Because the reliability of a-Si TFT is not as good as traditional Si-process,burn-in may reduce the performance of good circuits due to threshold voltage shift.Even burn-in destructs good circuits. VLV and IDDQ testing are well-known alternatives to burn-in because they are non-destructive and low cost. In our experiments, pseudo-NMOS NOR-NOR and multiplied-by-3 NOR-NOR programmableogic array are the circuits under test (CUTs), and the nominal voltage and VLV are 10V and 7V, respectively. Our experimental results show that VLV can screen out 2 unreliable circuits passing nominal voltage testing from 58 a-Si TFT circuits. Relatively, IDDQ is not effective in screening out unreliable circuits passing nominal voltageesting.
Subjects
amorphous silicon
thin-film transistor
very-low-voltage testing
IDDQ testing
reliability testing
Type
thesis
File(s)
No Thumbnail Available
Name
ntu-97-R95943117-1.pdf
Size
23.32 KB
Format
Adobe PDF
Checksum
(MD5):8a03de4bb5c3fbb85982e2662691b55d