A Multiple-Supply-Voltage Design Flow from Voltage Assignment to Floorplanning
Date Issued
2009
Date
2009
Author(s)
Lee, Wan-Ping
Abstract
As the CMOS technology enters the nanometer era, power dissipation is increasing severely and becomes a key challenge in nanometer chip design. If the increasing trend of power dissipation is still not tamed, the temperature of chips may be overheated, and further the functionality of the chips may fail. To moderate the increasing power dissipation, the multiple-supply voltage (MSV) design style recently has been extensively applied to mitigate dynamic-power consumption. Concisely, MSV is a trade-off between power saving and performance; in other words, we may sacrifice the performance whiling conserving the energy. Therefore, how to make a good trade-off becomes a key point for MSV design. MSV lowers supply voltages of non-timing-critical cells for power saving while raising ones of timing-critical cells for performance guarantee. Although the MSV design paradigm mitigates dynamic-power consumption, it brings many crucial design challenges at the same time, especially in voltage assignment, floorplanning, and power-ring synthesis. For such complicated designs, it is desirable to develop a methodology dealing with MSV designs.n this dissertation, we propose an MSV design flow from voltage assignment, through floorplanning, to power-ring synthesis and adjustment. This system consists of three parts: (1) voltage assignment and MSV-aware floorplanning,2) post-floorplanning voltage-island generation, and (3) MSV-aware post-floorplanning power ring synthesis.n this system, we first propose an effective voltage-assignment technique based on dynamic programming for MSV-aware technology mapping. For circuits without re-convergent fanouts, an optimal solution for the voltage assignment is guaranteed; (that is the power consumption is minimized while the timing constraint is satisfied.) for circuits with re-convergent fanouts, a near-optimal solution is obtained.fter the voltage assignment, we then generate a level shifter for each net that connects two blocks in different voltage domains, and perform power-network aware floorplanning for the MSV design. Next, we present a general formulation of the voltage-island generation problemhat considers level-shifter planning and power-network routing resources.o tackle the addressed problem, we employ an integer-linear programming (ILP) formulation which consists of1) level-shifter aware wirelength estimation to capture the timing overhead caused by level shifters, (2) voltage-island-clustering inequalities to avoid complicated constraint transformations, and (3) inequalities to capture the power-network routing-resource usage.nlike previous works that form the power rings as enclosing bounding boxes of voltage islands, we enable power rings alignment to the outer boundaries of voltage islands. With this new formulation, the power-ring estimation becomes more accurate during floorplanning,nd the power-ring synthesis becomes more practical after floorplanning. We therefore propose a linear-time voltage-island power-ring search algorithm to identify the power rings of voltage islands and then present a linear-time optimal power-ring corner-patching algorithm to minimize the number of corners in the power rings by using post-floorplanning whitespaces.
Subjects
physical design
floorplanning
multiple-supply voltage
low-power design
power-network synthesis
dynamic programming
integer-linear programming
contour searching
3D ICs
Type
thesis
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