10Gbps inductorless CDRs with digital frequency calibration
Journal
IEEE Transactions on Circuits and Systems I: Regular Papers
Journal Volume
55
Journal Issue
9
Pages
2514-2524
Date Issued
2008-10
Author(s)
Abstract
Two 10-Gb/s inductorless clock and data recovery (CDR) circuits using different gated digital-controlled oscillators (GDCO) are presented. A digital frequency calibration is adopted to save the power consumption and chip area. They have been fabricated in 0.18-mum CMOS process. By using the complementary gating technique, the first CDR circuit occupies an active area of 0.16 mm 2 and draws 36 mW from a 1.8 V supply. The measured rms jitter and peak-to-peak jitter is 8.5 ps and 42.7 ps , respectively. By using the quadrature gating technique, the second CDR circuit consumes an active area of 0.25 mm 2 and its power consumption of 56 mW. The measured rms jitter and peak-to-peak jitter is 3.4 ps and 21.8 ps, respectively. The power of the second CDR circuit is higher than that of the first one but its jitter is reduced.
SDGs
Type
journal article