A 10-bit High-Speed Low-Power Successive Approximation ADC
Date Issued
2009
Date
2009
Author(s)
Lin, Wen-Yu
Abstract
A 10b 80 MS/s CMOS Non-Binary SAR ADC using a non-constant radix binary search capacitor array is demonstrated in a standard 90-nm CMOS process. The ADC with the proposed capacitor array achieves higher conversion rate and lower power consumption compared to the prior non-binary SAR ADC works. Moreover, two-channel timeinterleaved method is utilized to achieve higher conversion rate.he prototype circuit exhibits an DNL of +0.9/-0.7 LSB and a INL of +1.2/-1.3 LSB. The SNDR and SFDR achieves 49.3 dB and 58.0 dB at 80 MS/s for Nyquist input frequency. The ADC consumes 2.87 mW at 1.2V supply and occupies an active chip area of 0.14 mm2. The FoM is 155.5 fJ/conv.-step at 80 MS/s.
Subjects
10-bit
Analog-to-digital Converter
Non-Binary SAR ADC
High-Speed
Low-Power
Type
thesis
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ntu-98-R95943126-1.pdf
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