Power Gating Strategies for Unified Shader Unit in GPU
Date Issued
2008
Date
2008
Author(s)
Chen, Yen-Ming
Abstract
As the technology continues to shrink, reducing leakage is critical to achieve energy efficiency. Previous works on low power GPU (Graphics Processing Unit) focuses techniques for dynamic power reduction, such as DVFS(Dynamic Voltage/Frequency Scaling), and clock gating. In this paper, we explore the potential of adopting architecture-level power-gating technique to reduce leakage power of GPU. Power-gating is to turn off a functional unit during its idle period. Due to different scene complexity, the required shader resources to achieve target frame rate varies among frames. Therefore, we adopt a history-based approach to predict required shader resources in a frame, and turn off redundant shader processors.he experimental results show that the proposed power-gating strategies achieve significant leakage reduction with negligible performance degradation. To achieve longer execution time and better energy utilization, power management is becoming more and more important issue to both batterypowered devices and tethered equipments. As CMOS technology evolving, leakage power will be the dominant source of power dissipation. In this paper, we explore possible redundant shader resources in modern GPU with unified shader architecture from exploiting power-gating perspective. We demonstrate observed redundant shader units from Frame-Level, which could be power-gated further to save leakage. In Frame-Level, we show that under unified shader architecture, there still exists redundant shader processors due to imbalance workload among frames. By deciding number of active shader processors dynamically using simple history-based prediction, we show that maximum of 15.2% shader leakage power could be saved while meeting performance requirement.
Subjects
GPU
Power-Gating
Leakage
SDGs
Type
thesis
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