Fast fault simulation for BIST applications
Resource
Test Symposium, 1995., Proceedings of the Fourth Asian
Journal
Test Symposium, 1995.
Pages
-
Date Issued
1995-11
Date
1995-11
Author(s)
Kung, Chen-Pin
Huang, Chun-Jieh
Lin, Chen-Shang
DOI
N/A
Abstract
Fault simulation is essential to design a high fault-coverage BIST. The simulation is characterized by combinational fault simulation and signature computation with a large amount of test patterns. In this paper, a fast fault simulator BISTSIM for BIST is developed. For the combinational fault simulation, a novel demand-driven logic simulation algorithm is proposed. Moreover, efficient fault propagation methods are incorporated into BISTSIM. The experimental results show that the proposed fault simulator delivers better performance than FSIM; about 2 to 3 times for circuits with a large number of test patterns. For signature evaluation of MISR to determine the aliasing, two efficient simulation methods, bit-array computation and parallel-pattern sequential simulation, are proposed. The resultant BISTSIM outperforms the fast fault simulator HOPE1.1 with an average speedup ratio of 10.
Type
journal article
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