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College of Electrical Engineering and Computer Science / 電機資訊學院
Electrical Engineering / 電機工程學系
Power-Efficient State Exchange Scheme for Low Latency SMU Design of Viterbi Decoder
Details
Power-Efficient State Exchange Scheme for Low Latency SMU Design of Viterbi Decoder
Journal
Journal of Signal Processing Systems (JSPS)
Journal Volume
68
Journal Issue
2
Pages
2803-2816
Date Issued
2012
Author(s)
Chun-Yuan Chu
AN-YEU(ANDY) WU
DOI
10.1007/s11265-011-0603-0
URI
https://scholars.lib.ntu.edu.tw/handle/123456789/427683
Type
journal article
