SiO 2 thickness dependence of C-V dispersion in stacked Al/HfO 2/SiO 2/4H-SiC capacitor
Journal
ECS Transactions
Journal Volume
45
Journal Issue
3
Pages
209-215
Date Issued
2012
Author(s)
Abstract
The impact of a thin interfacial SiO 2 layer inserted between HfO 2 and SiC for the improvement of electrical property was investigated. Regarding the material choice of dielectric on SiC, two issues will be presented in this work. One demonstrates the border trap induced C-V frequency dispersion when HfO 2 was directly deposited on SiC. The other deals with effect of carbon interstitial or bulk trap in SiC surface close to the SiC/SiO 2 interface. The thickness of SiO 2 interfacial layer is a critical issue. The defects induced by thicker SiO 2 layer would affect the inversion region of substrate. With adopted ultrathin SiO 2 (2 nm) layer between HfO 2 and SiC, the remarkable frequency dispersion can be significantly reduced. The leakage current with ultrathin SiO2 layer reduced about two orders as compared with only HfO 2 on SiC. The reliability of the device with ultrathin SiO 2 layer was also improved.
Type
conference paper