Signal/power integrity design strategy for low-cost package of high-speed memory I/O interfaces

Journal

IEEE Electron. Design Adv. Packag. Systems Symp.

Pages

1-4

Date Issued

2009-12

Author(s)

H.-H. Chuang

C.-J. Hsu

M.-Z. Hong

D. Hsu

R. Huang

L.-C. Hsiao

DOI

10.1109/EDAPS.2009.5404014

URI

http://scholars.lib.ntu.edu.tw/handle/123456789/352245

SDGs

[SDGs]SDG7

Type

conference paper