A fast settling low dropout linear regulator with single Miller compensation capacitor
Journal
IEEE Asian Solid-State Circuits
Pages
153-156
Date Issued
2005-11
Author(s)
Abstract
A 1.8-V, 150-mA fast settling low dropout linear regulator (LDO) with single Miller compensation capacitor is presented. By utilizing the digital-controlled dynamic bias circuit to track the output current, the proposed LDO provides fast settling time for the output capacitors with low and high equivalent series resistance (ESR). The proposed LDO has been fabricated in a 0.35-um 2P4M CMOS technology, and the active chip area is 480 um times675 um. The measurement results show the settling time of 4us can be achieved with 0.5% error for full load-current changes for both multilayer ceramic and electrolytic 1-uF output capacitors. Furthermore, the line and load regulations are 0.127%N and 40ppm/mA, respectively. The dropout voltage is 190mV in 150mA output current. The measured quiescent current is 45uA in 5V supply voltage without output current
SDGs
Type
conference paper