A 3~8GHz delay-locked loop with cycle jitter calibration
Journal
IEEE Transactions on Circuits and Systems II: Express Briefs
Journal Volume
55
Journal Issue
11
Pages
1094-1098
Date Issued
2008-10
Author(s)
Chi-Nan Chuang
Abstract
A 3-8 GHz delay-locked loop (DLL) with cycle jitter calibration is presented. To lower the operation frequency of a voltage-controlled delay line (VCDL), this DLL adopts the dividers, an edge combiner, and the multiple VCDLs. A duty cycle correction circuit is presented to maintain the output duty cycle of 50%. This DLL has been fabricated in 90-nm CMOS process. The measured peak-to-peak jitters at 8 GHz are 11.44 and 6.67 ps before and after calibration, respectively. The power dissipation at 8 GHz is 18 mW for a supply voltage of 1.2 V, and the measured output duty cycle variation is less than 3%. © 2008 IEEE.
Subjects
Calibration; Cycle jitter; Delay-locked loop (DLL); Duty cycle correction; Edge combiner
Other Subjects
Calibration; Jitter; Voltage dividers; 90-nm cmos; Delay-locked loops; Duty cycle correction; Edge combiners; Operation frequency; Peak-to-peak; Supply voltages; Voltage-controlled delay lines; Delay lock loops
Type
journal article