Design and Implementation of a 3.125-Gb/s Analog Equalizer for 10GBASE-LX4 Fiber-Optic Communication System
Date Issued
2004
Date
2004
Author(s)
Chen, Ping
DOI
en-US
Abstract
The exploring increasing of data rate in optical networks in recent years has created a major challenge for electronic circuits used at the interface of the optical physical layer links. Historically, the optical fiber used to be considered as a perfect channel. However, as the data rate increases above Gb/s, intersymbol interference (ISI) becomes an essential issue in digital communications, limiting the achievable transmission speed and distance over fibers.
Optical techniques can be used to compensate the impairments of optical fibers, with the advantage of requiring no high-speed electronic circuits. Nevertheless, electronic compensation is more flexible and economical, and may be a better choice. As to electronic compensation, digital or analog equalizers can be used. Digital (DSP based) equalization offers more accurate and higher performance comparing with analog counterpart. But the design of digital equalization has a bottleneck on the implementation of high-speed ADCs, which need large area and high power consumption. Consequently, pure analog equalizer is a more efficient solution.
Among different sub-standards of 10 Gigabit Ethernet (IEEE 802.3ae), 10GBASE-LX4 particularly attracts us. Its low-cost property has a substantially economical advantage on short-haul applications such as LANs. The use of WDM and 8B/10B coding scheme on 10GBASE-LX4 leads to a data rate of 3.125 Gb/s.
In this thesis, a 4-tap fractionally spaced analog FIR filter designed for 10GBASE-LX4 fiber-optic communication performs channel equalization. The continuous-time tap delay line is realized by a lumped LC ladder, providing linear and wideband characteristics. Fabricated in a standard 0.18-μm CMOS technology, the analog equalizer can successfully recover the 3.125- Gb/s random data transmitted over MMF channels while dissipating 2.3 mW from a 1.8-V power supply. Furthermore, an additional DLL is proposed to lock the tap delay time of the FIR filter, operating at 1.5625 GHz. The die sizes of two prototypes are 1.77 × 0.64 mm2 and 1.12 × 0.99 mm2, respectively.
Subjects
類比等化器
有限脈衝響應濾波器
光纖通訊
延遲鎖定迴路
百億位元乙太網路
Delay-Locked Loop
Analog Equalizer
Fiber-Optic Communication
FIR Filter
10 Gigabit Ethernet
Type
thesis