A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5 V full-swing BiCMOS dynamic logic circuit
Resource
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Journal
IEEE International Symposium on Circuits and Systems, 1994. ISCAS '94
Pages
-
Date Issued
1994-06
Date
1994-06
Author(s)
DOI
N/A
Abstract
This brief presents a BiCMOS dynamic multiplier, which is free from race- and charge-sharing problems, using Wallace tree reduction architecture and 1.5-V full-swing BiCMOS dynamic logic circuit. Based on a 1-μm BiCMOS technology, a 1.5-V 8 × 8 multiplier designed, shows a 2.3× improvement in speed as compared to the CMOS static one. © 1995 IEEE
Other Subjects
Adders; Bipolar transistors; Capacitance; CMOS integrated circuits; Electric power supplies to apparatus; Integrated circuit manufacture; Logic circuits; Logic gates; BiCMOS dynamic logic circuit; BiCMOS dynamic multiplier; Carry look ahead circuit; Charge sharing; Wallace tree reduction architecture; Multiplying circuits
Type
journal article
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