Networks on Chips: Structure and design methodologies
Journal
Journal of Electrical and Computer Engineering
Date Issued
2012
Author(s)
Abstract
The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors (CMPs) will contain hundreds or thousands of cores. Such a many-core system requires high-performance interconnections to transfer data among the cores on the chip. Traditional system components interface with the interconnection backbone via a bus interface. This interconnection backbone can be an on-chip bus or multilayer bus architecture. With the advent of many-core architectures, the bus architecture becomes the performance bottleneck of the on-chip interconnection framework. In contrast, network on chip (NoC) becomes a promising on-chip communication infrastructure, which is commonly considered as an aggressive long-term approach for on-chip communications. Accordingly, this paper first discusses several common architectures and prevalent techniques that can deal well with the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC. Finally, a novel bidirectional NoC (BiNoC) architecture with a dynamically self-reconfigurable bidirectional channel is proposed to break the conventional performance bottleneck caused by bandwidth restriction in conventional NoCs. © 2012 Wen-Chung Tsai et al.
SDGs
Other Subjects
Bandwidth restrictions; Bi-directional channels; Bus architecture; Bus interfaces; Chip Multiprocessor; Common architecture; Communication performance; Design issues; Design Methodology; Many-core; Many-core architecture; Multiprocessor system on chips; Network on chip; Networks on chips; On chip communication; On-chip bus; On-chip interconnection; Performance bottlenecks; Self-reconfigurable; Signal Integrity; System scalability; Traditional systems; Distributed computer systems; Program compilers; Reconfigurable architectures; Microprocessor chips
Type
journal article