Bias Temperature Instability of Low Temperature Polycrystalline Silicon Thin-Film Transistor
Date Issued
2007
Date
2007
Author(s)
YE, JIA-HONG
DOI
en-US
Abstract
Our thesis studies about bias temperature instability of low temperature polycrystalline silicon thin film transistors. In this thesis, we use different gate bias, stress gate bias time, temperature, and device structures to do our experiment. The different device structures are like LDD, channel types, gate stacks, and different width lengths etc. The goal of our experiment is to understand the electrical property of low temperature polycrystalline silicon thin film transistors. The electrical properties are like humps, threshold voltage shift, on current degrade and leakage current etc. Moreover, we want to build models of low temperature polycrystalline silicon thin film transistors about electrical properties. These models will be help for engineers who work about circuits.
Subjects
偏壓不穩定性
低溫複晶矽薄膜電晶體
BTI
LTPS TFT
Type
thesis
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