Closed-Form Breakdown Voltage Model for PD SOI NMOS Devices Considering Impact Ionization of Both Parasitic BJT and Surface MOS Channel Simultaneously
Journal
IEEE Transactions on Electron Devices
Journal Volume
49
Journal Issue
11
Pages
2016-2023
Date Issued
2002-11
Author(s)
S. C. Lin
Abstract
This paper reports a compact breakdown voltage model for partially depleted (PD) silicon-on-insulator (SOI) n-metal-oxide-semiconductor (NMOS) devices considering BJT/MOS impact ionization. Via the improved current conduction model considering BJT/MOS impact ionization this compact model provides an accurate prediction of the breakdown behavior of the PD SOI NMOS devices as verified by the experimental data and the MEDICI results. Based on the analytical model, when the gate voltage is lowered, the breakdown voltage decreases due to a stronger function of the parasitic BJT. In the subthreshold region, the breakdown voltage increases at a decreased gate voltage due to a weaker function of the parasitic BJT.
Subjects
Compact model; Complementary metal-oxide-semiconductor (CMOS); Partially depleted (PD); PD breakdown voltage; Silicon-on-insulator (SOI); SPICE
Type
journal article