Memory Bandwidth Reduction Technique with Visibility Testing Engine for 3D Graphics Rendering Systems
Date Issued
2006
Date
2006
Author(s)
Wu, Chi-Ling
DOI
en-US
Abstract
In recent years, 3D graphics industry is growing rapidly, and the requirements for graphics hardware become larger than before. With the flourishing development of entertainment industry, 3D graphics applications become widespread. However, since the models and scenes become more and more complex and the rendering quality requirement is getting higher and higher, the 3D graphics rendering systems will need to process more and more data and suffer from high external memory bandwidth.
In this thesis, we propose a hardware-oriented visibility testing algorithm to reduce the external memory bandwidth. In the algorithm level, the proposed visibility testing algorithm adopts coverage masks to reduce the visibility data bandwidth and easily integrates antialiasing with oversampling. Beside, coverage masks can construct a hierarchical structure, which can speed up the visibility testing progress. On the other hand, the visibility tests are done during rendering without occlusion queries. In this algorithm, the incoming primitives are sorted in the front-to-back order because of coverage mask adoption. For static scenes and models, they are usually sorted with BSP trees and are accelerated in Z-buffer systems. But with our proposed algorithm, not only accelerating but also reducing more external memory bandwidth can be achieved with sorted primitives. Thus the proposed visibility algorithm can be seen as an accelerator for static scenes or models.
In architecture level, the proposed algorithm can be integrated into 3D graphics hardware rendering systems. The proposed hardware-oriented visibility testing algorithm can be implemented by hardware with scalability. With scalability, the proposed rendering system can be easily extended to various graphics applications.
The experimental results shows that $80\%$ of the external memory bandwidth can be reduced without antialiasing, and $97\%$ of reduction can be achieved with antialiasing. The prototype chip of the proposed 3D graphics rendering system with visibility testing engine is fabricated with TSMC 0.18um 1P6M technology, where the chip size is 2.57x2.57 mm^2.
Subjects
三維圖學渲染
圖學硬體
可見度
3D graphics rendering
graphics hardware
visibility
Type
thesis
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