Modeling the Gate Tunneling Current Effects of Sub-100nm NMOS Devices with an Ultra-thin (1nm) Gate Oxide
Journal
International Electron devices Semiconductor Technology Conf (IEDST)
Date Issued
2007-06
Author(s)
Abstract
This paper reports the modelling the gate tunneling current effects of sub-100nm NMOS devices with an ultra-thin (1nm) gate oxide. As verified by the experimentally measured data, the compact gate tunneling current model considering the distributed effect provides an accurate prediction of the gate, source, and drain currents for the device biased in triode and saturation regions. Based on the compact model, the negative gate current could be successfully explained as a result of the opposite direction of the local vertical electric field in the gate oxide near drain.
Type
conference paper