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College of Electrical Engineering and Computer Science / 電機資訊學院
Electrical Engineering / 電機工程學系
Modeling the Gate Tunneling Current Effects of Sub-100nm NMOS Devices with an Ultra-thin (1nm) Gate Oxide
Details
Modeling the Gate Tunneling Current Effects of Sub-100nm NMOS Devices with an Ultra-thin (1nm) Gate Oxide
Journal
International Electron devices Semiconductor Technology Conf (IEDST)
Date Issued
2007-06
Author(s)
JAMES-B KUO
DOI
10.1109/edst.2007.4289773
URI
http://scholars.lib.ntu.edu.tw/handle/123456789/333621
Type
conference paper
