Insights into Threshold Voltage Variability in Negative Capacitance Junctionless Transistor
Journal
IEEE Journal of the Electron Devices Society
Start Page
1
End Page
1
ISSN
2168-6734
Date Issued
2024
Author(s)
Abstract
This work investigates the statistical variability of threshold voltage (σVth) and its sensitivity to critical geometrical parameters in negative capacitance (NC) junctionless (JL) and conventional JL transistors through quantum-corrected TCAD simulations. Threshold voltage variability (σVth) considering the statistical variation is assessed by varying the gate length, film thickness, channel doping, equivalent oxide thickness, and ferroelectric thickness. Results showcase σVth owing to the process-induced variation in the device parameters can be reduced considerably by integrating the ferroelectric layer in the gate stack of JL devices. Among all the device parameters, variability analysis shows that σVth degrades more against the variation in film, equivalent oxide, and ferroelectric thicknesses. As channel doping is critical to NCJL devices, we showcase that designing the NCJL transistors with moderate channel doping of 1018 cm−3 considerably lowers the σVth against the device parameter variation. This work features the systematic methodology to lower the process-induced Vth variability in NCJL devices while highlighting the potential significance of moderately doped channels at shorter technology nodes.
SDGs
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Type
journal article