Design of an All-CMOS Low-temperature-drift Voltage Reference with Assisted-one-temperature-point Trim
Date Issued
2015
Date
2015
Author(s)
Ho, Kuan-Lin
Abstract
Voltage reference (VR) is required in integrated circuits for providing a stable voltage, which is ideally immune to temperature, supply and process variations. It undoubtedly plays a crucial role in analog circuit applications. This thesis proposes an all-CMOS voltage reference with assisted-one-temperature -point trim in a 40-nm CMOS technology that is functional from 0.8-V supply. Conventionally, BJT-based references are commonly used, but a BJT consumes at least 0.75V headroom. Thus, they are not suitable for advanced technologies because of supply scaling. Previously solutions include BJT-free designs, but they exhibit worse temperature characteristics, or complex trimming methodology is demanded to achieve a reasonable temperature coefficient (TC). In this work, one-temperature-point trim on bias makes MOS exhibit better temperature characteristics. Thus, an all-MOS circuit topology featuring low temperature drift can be achieved with simple trimming procedures. The chip is fabricated in a TSMC 40-nm CMOS technology. It works down to a supply of 0.8 V and occupies 0.049 mm2. Total 8 samples was measured from -10˚C to 100 ˚C. Measurement results show that the average TC is about 30 ppm/˚C and 3σ spread is only 0.14 %. Also, PSR of -48 dB at a low frequency is attained, and line sensitivity (LS) is below 1.8 %/V.
Subjects
Voltage reference
temperature compensation
assisted-one-temperature-point (A-OTP) trim
Type
thesis
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