Parallel Non-Integer Multiple-Cell-Height Node Remapping
Journal
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
Start Page
1
End Page
9
ISBN (of the container)
979-833151560-7
Date Issued
2025-11-20
Author(s)
Abstract
The fast-growing complexity of VLSI circuits with non-integer multiple-cell-height (NIMCH) standard cells poses new challenges for timing-aware node remapping. The existing remapping flow suffers from significant computational overhead due to exhaustive enumeration of all node-to-gate mapping combinations, including nodes and their fanin nodes. To remedy this inefficiency, we propose a novel NIMCH node remapping flow consisting of the following two schemes: a parallel longest-path-first scheme and an iterative minimum-slack-first scheme. Both schemes prioritize timing-critical nodes to reduce runtime. Moreover, the first scheme enables parallel execution, substantially accelerating the remapping process. Experimental results show that our proposed method achieves an average runtime speedup of 5.58X compared to the state-of-the-art approach, while preserving placement quality. The improved efficiency and scalability of our flow make it well-suited for large-scale physical design applications where rapid timing closure is essential.
Event(s)
44th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2025
Publisher
Institute of Electrical and Electronics Engineers Inc.
Type
conference paper