720×480 30fps efficient prediction core chip for stereo video hybrid coding system
Journal
2005 IEEE Asian Solid-State Circuits Conference
Pages
529-532
Date Issued
2006
Author(s)
Abstract
The chip design of prediction core in the stereo video hybrid coding system is implemented with 0.18 μm 1P6M technology by TSMC. The die size is 4.53 mm2. This IC can can achieve real-time requirement under the operating frequency of 81 MHz for 30 D1 frames per second (fps) in the left and the right channel simultaneously, with ME/DE search range of [-64, +63] in horizontal direction and [-32, +31]/[-16, +15] in vertical direction. Compared with the hardware requirement for implementation of full search block matching algorithm (FSBMA), only 11.5% on-chip SRAM and 1/30 amount of PEs are needed. It shows that the hardware cost is quite small. © 2005 IEEE.
Type
conference paper