Via-based Redistribution Layer Routing for InFO Packages with Irregular Pad Structures
Journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Date Issued
2022
Author(s)
Abstract
The integrated fan-out (InFO) wafer-level chip-scale package is introduced for modern system-in-package designs with larger I/O counts, higher interconnection density, and small form factors. A redistribution layer (RDL) in an InFO package is an extra metal layer for inter-chip connections, and RDL routing is crucial for achieving desired inter-chip connections. In a high-density InFO package, multiple RDLs with flexible vias are often adopted. To integrate chips of different technology nodes into one package, irregular pad structures need to be considered; however, no published RDL routing work considers flexible vias or irregular pad structures. This paper formulates a new RDL routing problem with unified-assigned pad pairs on a via-based multi-layer multi-chip InFO package with irregular pad structures, and presents the first algorithm for this problem. The algorithm consists of a preprocessing stage, three routing stages, and a layout optimization stage. The preprocessing stage analyzes routing resources and potential routing congestion. The first routing stage performs layer assignment based on a weighted maximum planar subset of chords algorithm to route inter-chip nets concurrently. The second routing stage constructs a 3D routing graph based on partitioned octagonal tiles to handle the irregular layout structure and applies A*-search to route remaining inter-chip nets. The third routing stage transforms a routing graph into a network-flow model to perform concurrent routing for chip-to-board nets by applying the minimum cost maximum flow algorithm. Finally, we develop an efficient linear-programming-based layout optimization algorithm to find desired solutions. Experimental results show that our router can achieve 100% routablility for all benchmarks under limited RDLs, while the previous state-of-the-art work cannot. IEEE
Subjects
Flexible Via; Flip-chip devices; Integrated Fan-Out Wafer-Level Chip-Scale Package; Irregular Pad Structure.; Layout; Metals; Physical Design; Planning; Redistribution Layer Routing; Routing; Routing; Topology; Wires
Other Subjects
Chip scale packages; Flow graphs; Graphic methods; Linear programming; Microprocessor chips; Routers; System-in-package; Fan Out; Flexible via; Flip-chip devices; Integrated fan-out wafer-level chip-scale package; Irregular pad structure.; Layout; Pad structures; Physical design; Redistribution layer routing; Redistribution layers; Routings; Wafer-level chip scale packages; Flip chip devices
Type
journal article