The Strain and Stress Simulation for 5nm CMOS Technology Node and Beyond
Date Issued
2009
Date
2009
Author(s)
Lai, Chao-Yun
Abstract
Transistor scaling down has been the principal factor in driving CMOSFET performance improvement for more than thirty years. Approaching the fundamental limits of transistor scaling leads the industry and the research community to actively search for alternative solutions. The use of strained Si obtained by stress engineering seems to be one solution to achieve transistor performance improvements.ne of stress engineering is contact etch stop layer (CESL), since the 90nm CMOS technology node, the CESL is used as a stress-engineering booster that enables transistor improvement, and the CESL consists in a nitride layer used to stop the etching of the metallic contact.he other one of stress engineering is stress memorization technique (SMT), the SMT is one of the few strain techniques for N-FET performance enhancement, and it has been a necessary technique in recent high-performance technology not only for conventional poly-gates, but also for MIPS (Metal Inserted Poly-silicon Stack) and metal gates. There are two major theory support SMT, one is plastic deformation model and the other one is poly-gate volume expansion.inally, other simulations for strain enhancement techniques are discussed. Such as the influence of CESL thickness and poly spacing, decomposition of the intrinsic stress, the Dopant Confinement Layer (DCL) technique, Multi-SMT, SMT in source and drain, the insulating halo for shallow trench isolation (STI).
Subjects
CESL
SMT
plastic deformation model
poly-gate volume expansion
DCL
insulating halo
STI
Type
thesis
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