CMOS four-quadrant multiplier using bias offset crosscoupled pairs
Journal
Electronics Letters
Journal Volume
29
Journal Issue
20
Pages
1737-1738
Date Issued
1993
Author(s)
Abstract
A CMOS four-quadrant multiplier using bias offset crosscoupled pairs is presented. Simulation results show that for a power supply of ±5 V, the linearity error is less than 1% over a ±2.5 V input range. The effect of mobility reduction is also analysed. The results will be useful in analogue signal processing applications.
SDGs
Type
journal article