A 144mW 161Mpixels/s Tensor Display Processor for 3D Virtual Reality
Journal
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Journal Volume
69
Start Page
414-416
ISBN
[9798331589363]
Date Issued
2026-02-15
Author(s)
Abstract
This work presents a 3D display processor that converts the focal stack to tensor display. Algorithm-architecture co-optimization is applied to reduce the computational complexity and hardware complexity. It achieves the maximum throughput of 161 Mpixels/s (equivalent to 87 fps at HD resolution) at a clock frequency of 200 MHz, with normalized energy consumption of 0.9nJ/pixel, and a PSNR of 23.7 to 24.8dB.
Event(s)
2026 IEEE International Solid-State Circuits Conference, ISSCC 2026
Publisher
IEEE
Type
proceedings-article