A 6.7MHz-to-1.24GHz 0.0318mm2fast-locking all-digital DLL in 90nm CMOS
Journal
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Journal Volume
55
Pages
244-245
Date Issued
2012
Author(s)
Abstract
Delay-locked loops (DLLs) are widely adopted for clock generation and synchronization in high performance digital systems. The design of analog DLLs has become a challenge due to the trends associated with CMOS scaling, namely, high leakage current, low supply voltage, etc. Consequently, many designers have shifted their focus to digitally-assisted or all-digitally implemented DLLs, which are easier to design for wide range and fast-locking requirements. Due to the need for wide operating frequency range applications in all-digital DLLs (ADDLLs), many delay cells are normally deployed. As a result, a large portion of the die area is consumed by the delay cells. To address this issue, we develop a phase-tracing delay unit (PTDU) technique to reduce delay-cell usage and achieve low area and low power. In this paper, a 6.7MHz-to-1.24GHz 0.0318mm 2 fast-locking ADDLL based on the PTDU method is realized in 90nm CMOS technology.
SDGs
Type
conference paper