Power estimation scheme for lowpower oriented biomedical SoC extended to very deep submicron technology
Journal
ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing
Pages
749-752
Date Issued
2011
Author(s)
Abstract
This paper introduces a power estimation scheme and generated results of SoC (System-on-Chip) fabricated with different process nodes extending to very deep submicron tech nology. Different power modeling strategies are used to estimate power for analog and digital circuits. According to the analysis results, ultra low power analog components are key to successful biomedical SoC design if more advanced fabrication technology is utilized. Meanwhile, the digital part should be designed barely enough to serve the target application. Integrating more dedicated digital hardware accelerators can further reduce the total power consumption by lowering the working frequency of system processor. The goal of this paper is to provide a quantitative scheme to estimate the power consumption when SoC is fabricated with different process technologies. Then a suitable technology could be selected to manufacture the SoC for biomedical usage.
SDGs
Type
conference paper