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College of Electrical Engineering and Computer Science / 電機資訊學院
Electrical Engineering / 電機工程學系
An efficient multi-level partitioning algorithm for VLSI circuits
Details
An efficient multi-level partitioning algorithm for VLSI circuits
Journal
IEEE International Conference on VLSI Design
Journal Volume
2003-January
Pages
70-75
Date Issued
2003
Author(s)
Cherng, J.-S.
SAO-JIE CHEN
DOI
10.1109/ICVD.2003.1183117
URI
http://www.scopus.com/inward/record.url?eid=2-s2.0-77952269571&partnerID=MN8TOARS
http://scholars.lib.ntu.edu.tw/handle/123456789/303247
SDGs
[SDGs]SDG10
Type
conference paper