An efficient multi-level partitioning algorithm for VLSI circuits
Journal
IEEE International Conference on VLSI Design
Journal Volume
2003-January
Pages
70-75
Date Issued
2003
Author(s)
Cherng, J.-S.
Abstract
In this paper, a new multi-level bipartitioning algorithm MLP, which integrates a clustering technique and an iterative improvement based partitioning process, is proposed to enhance the stability and the quality of partitioning results. The proposed clustering algorithm is used to reduce the partitioning complexity and improved the performance of partitioning. To generate a high-quality partitioning solution, a module migration based partitioning algorithm MMP is also proposed as the based partitioner for the MLP algorithm. The MMP algorithm implicitly promotes the move of clusters during the module migration processes by paying more attention to the neighbors of moved modules, relaxing the size constraints temporarily during the migration process, and controlling the module migration direction. Experimental results obtained show that the MLP algorithm generates high-quality partitioning results. The MLP algorithm outperforms MELO and CDIP/sub LA3/ by 23% and 10%, respectively and is competitive with hMetis and ML/sub c/ which have generated better results than many recent state-of-the-art partitioning algorithms.
SDGs
Type
conference paper