Unified convolutional/turbo decoder architecture design based on triple-mode MAP/VA kernel
Resource
Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on
Journal
IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS
Pages
1073-1076
Date Issued
2004-12
Date
2004-12
Author(s)
DOI
N/A
Abstract
We proposed triple-mode MAP/VA timing charts that can run two different algorithms at the same time by complementing each other. Then, we address the implementation of a reconfigurable architecture for unified convolutional/turbo decoder design. According to the triple-mode MAP/VA timing chart and by merging some similar modules in both the Viterbi decoder and the log-MAP turbo code decoder, we build one unified component decoder with both of these two functions. Besides, in order to conform to the advance communication standard, our decoder can also perform as a reconfigurable trellis decoder. That is, our design meets the requirement of the multi generator polynomial in the convolutional code specification.
Type
conference paper
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